1. Field of the Invention
This invention generally relates to a radio frequency (RF) switch that is used for a radio frequency device such as a mobile telecommunications device, and more particularly, to the radio frequency switch on which multiple FETs are connected in series.
2. Description of the Related Art
In recent years, an RF switch having multiple ports (SPNT: Single Pole N-Through: N denotes the number of ports) has been employed in a mobile telephone unit, which communicates over multiple carrier signals. The RF switch includes a field-effect transistor (FET) composed of compound semiconductors. The RF switch is required to have a low harmonic performance, more specifically −70 dBc or less, to a fundamental harmonic of a transmitting signal. In order to suppress a harmonic component at a low level, the FET is required to improve linearity in the on-state resistance and to have an excellent off-state power.
In order to improve the off-state power, commonly, the FETs are connected in series at M stages. FIG. 1 shows an example of FETs connected in series at M stages. In the case where all the FETs are off, an RF signal passes through an RF signal line. In the case where all FETs are on, the RF signal passes across the FETs to the ground. In the case where all the FETs connected in series at M stages are off, each stage receives a voltage of 1/M theoretically. If the voltage of the RF signal is denoted by V, the voltage of V/M is applied to each of the FETs. However, in fact, each FET is affected by a parasitic capacitance to ground of the FET, which is denoted by Cp in FIG. 2. Referring to FIG. 2, Cds denotes a capacitance between the drain and source of each FET, and Cg denotes a capacitance between the gate and source or between the gate and drain of each FET. Referring to FIG. 3A, an impedance Zcp of the parasitic capacitance Cp to ground is connected to the impedance Z of the FET at each stage. Accordingly, as shown in FIG. 3B, the impedance at each stage is not equal (Z→Z′(<Z)). Because of the aforementioned impedance inequality among the stages, a voltage V1 is applied to the FET (the impedance Z) closest (or directly connected) to the RF signal line, in which the voltage V1 is greater than a voltage V2 (<V1) applied to the other stages (impedance Z′ (<Z)). This results in a problem in that a handling power becomes smaller than a value calculated from the following logical formula 1.Pmax=2[M(Vp−Vcont)]2/Zo  (Formula 1)
Here, M denotes the number of stages of the series connection, Vp denotes a pinch-off voltage at which the FET turns off from on or vise versa, Vcont is a control voltage applied to the gate of the FET, Zo is a system impedance, and Pmax is the maximum handling power.
In order to solve the aforementioned problem, as shown in FIG. 4, Mitchell B. Shifrin, et al. propose to add capacitances C1 and C2 to the stages to thus modify the parasitic capacitance to ground (see Mitchell B. Shifrin, et al., “Monolithic FET structures for High-Power Control Component Applications”, IEEE Transactions on Microwave Theory and Technique, Vol. 37, No. 12, December 1989, pp. 2134-2141 (hereinafter referred to as Document 1)). By connecting the capacitances C1 and C2 in parallel with the FET, the impedance is equally divided at each stage and the high-frequency voltage V is equally divided into V1, V2, and V3. (V1=V2=V3).
Referring to FIGS. 5A and 5B, Japanese Patent Application Publication No. 8-70245 (hereinafter referred to as Document 2) and Japanese Patent Application Publication No. 9-8621 (hereinafter referred to as Document 3) disclose that a capacitance, Ca in FIG. 5A and another capacitance Cb in FIG. 5B, are respectively added between the source or drain and the gate, and the voltage divided between the gate and source is intentionally shifted. FIG. 6A shows changes of a voltage difference between V1 and V2 (V1−V2) and another voltage difference between V2 and V3 (V2−V3) in a case where the capacitances Ca and Cb are not added. FIG. 6B shows FIG. 6A shows changes of the voltage difference (V1−V2) and the voltage difference (V2−V3) in a case where the capacitances Ca and Cb are added as shown in FIGS. 5A and 5B. Here, V1 is the voltage of the RF signal, V2 is the voltage at a connection point between the capacitance Ca and the gate, and V3 is the voltage at a node that connects the two FETs in series. A symbol Vp in FIGS. 6A and 6B denotes the pinch-off voltage. The use of the additional capacitances Ca and Cb shifts the voltage divided between the gate and source. Even if the RF voltage has a large amplitude, the voltage can be offset so that the gate voltage may not exceed the pinch-off voltage Vp. Thus, the handling power is improved.
However, the conventional technique disclosed in Document 1 and shown in FIG. 4 has a problem in which a signal is leaked through the capacitances C1 and C2. This leakage current degrades isolation at the time of switching off. Costs are increased in the capacitance formation process. In addition, in case where the capacitances C1 and C2 have a low breakdown voltage, the surge resistance such as ESD may be degraded. Generally, a capacitance on an MMIC has a low breakdown voltage.
The conventional techniques disclosed in Documents 2 and 3, shown in FIGS. 5A and 5B, also have the same problem as that in Document 1. Additionally, there is still another problem in that the FETs are required to have a high breakdown voltage, as compared to the circuit without the capacitances Ca and Cb.
Further, in recent years HEMT has been used instead of MESFET in order to reduce the insertion loss of the switch. Generally, when the on-state resistance is lowered, the breakdown voltage tends to be lowered due to a highly concentrated channel layer. Therefore, it is no longer possible to solve the above-mentioned problems with the conventional techniques disclosed in Documents 1 through 3, which have the problems in terms of the breakdown voltages.